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Vendor-independent, scalable rules (MOSIS SCMOS Rules) Rules Updated: May 11, 2009 1. Introduction This document defines the official MOSIS scalable CMOS (SCMOS) layout rules. It supersedes all previous revisions. fabrication processes available through MOSIS. The designer works in the abstract SCMOS wants the design to be fabricated in. MOSIS maps the SCMOS design onto that process, generating the true logical layers and abso lute dimensions required by the process vendor. The designer can often submit exac tly the same design, but to a different fabrication process or feature size. MOSIS alone handles the new mapping. By contrast, using a specific vendor's layers and design rules ("vendor rules") will yield a design which is less likely to be directly portable to any other process or feature size. Vendor rules usually need more logical layers than the SCMOS rules, even though both learning curve for that one process, more interactions to worry about, more complex design support required, and longer layout development times. Port ing the design to a new process will be burdensome. SCMOS designers access process-specific fe atures by using MOSIS-provided abstract poly would use the MOSIS-provided second-poly abstract layer, but must then submit to a . In the same way, designers may access layout. Vendor rules may be more appropriate when direct control over analog circ added investment in development time and loss of design portability is clearly justified. However the advantages of using SCMOS ru les may far outweigh such concerns, and should be considered. 1.1 SCMOS Design Rules different fabrication processes as se miconductor technology advances. Each design has a tech nology-code associated with the layout file. Each technology-code may have one or more associated options adde d for the purpose of sp At the time of this revision, MOSIS is offeri ng CMOS processes with feature sizes from 1.5 micron to 0.18 micron. 2. Standard SCMOS bulk CMOS process with enhancement-mode 2.1. Well Type The Scalable CMOS (SC) rules support both -well and -well processes. MOSIS recognizes three base technology codes that process selected. SCN specifies an -well process, SCP specifies a -well process, and SCE indicates that the designer is willing to utilize a process of either -well or -well. An SCE design must provide both a drawn -well and a drawn -well; MOSIS will use the well that corresponds to the selected process and ignore the other well. As a convenience, SCN and SCP designs may also include the other well ( -well in an SCN design or -well in an SCP design), but it wi ll always be ignored. MOSIS currently offers only -well processes or foundry-de that from the design an d process flow standpoints are equivalent to -well processes. These twin-well processes may have options (deep -well) that provide independently isolated -wells. For all of these processes at this time use the technology code SCN. SCP is currently not supported, and SCE is treated exactly as SCN. 2.2. SCMOS Options SCMOS options are used to designate projects that use additional layers beyond the is appended to the basic technology-code. Pl ease note that not all possible combinations are available. The current list is shown in Table 1. MOSIS has not issued SCMOS design rules for some vendor-suppo rted options. For example, any designer using the SCMOS rule non-SCMOS layers should be addressed through the MOSIS Online Support System Designation Electrode Adds a second polysilicon layer (poly2) that can serve of a poly capacitor or (1.5 micron only) as a gate for transistors Adds electrode (as in E option), plus layers for vertical NPN transistor pbase layers layers layers Linear Capacitor Adds a cap_well layer for linear capacitors PC Poly Cap Adds poly_cap, a different layer for linear capacitors DEEP micron processes (see section 2.4) For options available to specific processes, see Tables 2a and 2b. Table 2a: MOSIS SCMOS-Compatible Mappings Foundry Lambda (micro- C5F/N (0.5 micron -well) SCN3M, SCN3ME 3.3 V/5 V) SCN4ME SCN4M Table 2b: MOSIS SCMOS_SU BM-Compatible Mappings Foundry Lambda (micro- C5F/N (0.5 micron -well) SCN3M_SUBM, SCN3ME_SUBM TSMC Polycided, 3.3 V/5 V) SCN4ME_SUBM TSMC Silicided, 3.3 V/5 V) SCN4M_SUBM TSMC V/3.3 V) SCN5M_SUBM TSMC V/3.3 V) SCN6M_SUBM Table 2c: MOSIS SCMOS_DEEP-Compatible Mappings Foundry Lambda (micro- TSMC 0.12 TSMC 0.09 2.3. SCMOS-Compatible Processes MOSIS currently offers the fabrication proce sses shown above in Tables 2a, 2b, and 2c. For each process the list of appropriat e SCMOS technology-codes is shown. 2.4. SCMOS_SUBM and SCMOS_DEEP Rules The SCMOS layout rules were historically developed for 1.0 to 3.0 micron processes. To take full advantage of sub-micron processes, the SCMOS rules were revised to create SCMOS_SUBM. By increasing the la se that didn't shrink as fast in practice as did the overall scheme of things), the sub-micron rules allow for use of The SCMOS_SUBM rules were revised again at typical deep submicron processes, creating the SCMOS_DEEP variant. Table 3a: SCMOS and SCMOS Sub-mi SCMOS SCMOS 1.1, 17.1 1.2, 17.2 (different potential) Well overlap (space) to transistor Poly space 5.3, 6.3 Contact space Contact to Poly space to Poly Poly2 width Poly2 overlap Space to Poly2 contact Poly2 contact space Table 3b: SCMOS Sub-micron and SCMOS Deep Differences SCMOS SCMOS DEEP Poly space Poly space gate extension Active extension of Contact Select width and space (p+ to p+ or n+ to n+) 5.3, 6.3 Contact spacing 2 x 2 3 x 3 Via4 overlap 3 x 3 4 x 4 A user design submitted to MOSIS using the SCMOS rules can be in either Calma GDSII interchangable. Note that all submitted CIF and GDS files have already been scaled before specifications of GDS and CIF, refer to [2] and [1] respectively. In GDS format, a design layer is specifie d as a number between 0 and 255. MOSIS SCMOS now reserves layer numbers 21 through 62, incl usive, for drawn layout. Layers 0 through 20 plus layers 63 and above can be used by de signers for their own pu rposes and will be ignored by MOSIS. Users should be aware that there is only one contact mask layer, although several of SCMOS layers is shown in Table 4, along with a list by technology code in Table 5. Table 4: SCMOS Layer Map N_WELL CWN CWP SCPxx CAP_WELL CWC SCN3MLC ACTIVE THICK_ ACTIVE SCN4M (TSMC only), SCN4ME, SCN5M, SCN6M CBA SCNA POLY_CAP1 CPC CPG BLOCK CSB SCN3M, SCN4M (TSMC only), SCN5M, SCN6M N_PLUS_ SELECT P_PLUS_ SELECT CSP CEL SCNE, SCNA, SCN3ME, SCN4ME IMPLANT CHR SCN3ME CONTACT CCC CCG CONTACT CCP Can be replaced by CONTACT ACTIVE_ CONTACT CCA Can be replaced by CONTACT POLY2_ CONTACT CCE SCNE, SCNA, SCN3ME, SCN4ME Can be replaced by CONTACT. CM1 CMF CM2 CMS SCN3M, SCN3ME, SCN3MLC, SCN4M, SCN4ME, SCN5M, SCN6M CM3 CMT SCN3M, SCN3ME, SCN3MLC, SCN4M, SCN4ME, SCN5M, SCN6M SCN4M, SCN4ME, SCN5M, SCN6M CM4 CMQ SCN4M, SCN4ME, SCN5M, SCN6M CAP_TOP_ CTM SCN5M. SCN6M CVQ SCN5M, SCN6M CM5 CMP SCN5M, SCN6M SCN6M CM6 SCN6M DEEP_ N_WELL CDNW SCN5M, SCN6M COG PADS Optional non-fab layer used solely to highlight the bonding pads. Table 5: Technology-code Map Technology with link to layer map SCNA N_well, Active, N_select, P_select, Poly, Poly2, Contact, Pbase, N_well, Active, N_select, P_select, SCN3M N_well, Active, N_select, P_select, Poly, Hi_Res_Implant, Contact, SCN3ME N_well, Active, N_select, P_select, Poly, Poly2, Hi_Res_Implant, SCN3MLC N_well, Cap_well, Active, N_select, P_select, Poly, Silicide block, SCN4M N_well, Active, Thick_Active (TSMC only), N_select, P_select, Poly, SCN4ME N_well, Active, Thick_Active, N_select, P_select, Poly, Poly2, SCN5M N_well, Active, Thick_Active, N_select, P_select, Poly, Silicide block, SCN6M N_well, Active, Thick_Active, N_select, P_select, Poly, Silicide block, Contact, Metal1, Via, Metal2, Vi Many fine-featured processes utilize CMP (Chemical-Mechanical Polishing) to achieve planarity. Currently, for MOSIS, the ON Semi smaller) processes are in this category. Effective CMP requires that the variations in feature density on layer be restricted. 5. Process-Induced Damage Rule s (otherwise known as "Antenna Rules"): General Requirements The "Antenna Rules" deal with process indu ced gate oxide damage caused when exposed large to cause Fowler Nordheim current to fl ow through the thin oxide. Given the known process charge fluence, a figure of exposed conductor area to transistor gate area ratio is requirements for the fabricator. Failure to consider antenna rules in a design may lead to either reduced performance in transistors exposed to process induced damage, or may lead to total failure if the antenna rules are seriously violated. 6. Support for Arbitrary Via Placeme Some processes have restrictions on the placem ent of vias relative to contacts (rule 8.4) and/or relative to poly an d active edges (rule 8.5). Ot placement of vias over these lower features. The placement of vias directly over contacts or other, lower vias is known as "stacked vias." Table 6: Applicability of Rules 8.4 and 8.5 Technology code with link to layer map SCN3M SCN3ME SCN4M TSMC 0.35 SCN4ME TSMC 0.35 SCN5M TSMC 0.25 SCN6M TSMC 0.18 MOSIS Scalable design rules require that layout is on a lambda grid. Any other gridding information may change without warning. We ss a design regardless The fracture process puts all its data onto a grid. As an example, the mask grid size in the case of the TSMC 0.35 micron process is 0. 0125 micron on the critical layers and 0.025 micron on the others, and all points in your layout that do not fall onto these grid points are "snapped" to the nearest grid point. Obviousl y, half a grid is the largest snap distance, applied to points that fall neatly in the middle. The 0.025 fracture grid is lambda for SCN4ME_SUBM and lambda for SCN4ME. 8. PADS Layer MOSIS has defined an optional PADS layer to help users tell MOSIS which glass openings cuts that you want MOSIS to use in generati ng an automated bonding for your project. When used, PADS should match the glass cuts just the selected glass cuts. When the PADS layer is not present, MOSIS w appear to be bonding pads and which do not. For the vast majority of layouts, the PADS layer is unnecessary. References [1] C. Mead and L. Conway, Introduction to VLSI Systems , Addison-Wesley, 1980 [2] Cadence Design Sy GDSII Stream Format Manual , Feb. 1987, Release 6.0, Documentation No. B97E060 [3] N. H. E. Weste Principles of CMOS VLSI Design: A System , Addison-Wesley, 2nd edition, 1993 for SCMOS_DEEP (and SUBM) The DEEP_N_WELL layer provides access to the DNW layer in the TSMC 0.18 and 0.25 processes. This provides a laye SCMOS DEEP 31.1 Minimum Width, Deep_N_Well 31.2 Minimum Spacing, Deep _N_Well to Deep_N_Well 31.3 Minimum extension, N_Well beyond Deep_N_Well edge 31.4 Minimum overlap, N_Well 31.5 Minimum spacing, Deep_N _Well to unrelated N_Well 31.6 Minimum spacing, N+Active in isolated P-well, to N_Well 31.7 Minimum spacing, external N+Active to Deep_N_Well Minimum spacing, P+Active in N_Well to its SCMOS DEEP 12 The capacitor well described in this and the next rule only apply to SCN3MLC and SCN3MLC_SUBM technology codes manufactured on an Agilent/HP SCMOS DEEP 12 18 6 6 These rules illustrate the construction of a linear capacitor in a capacitor well. overlapped poly and active. The active area is electrically connected to the cap well SCMOS DEEP 3 Minimum poly extension of active Minimum active overlap of poly Minimum poly contact to active 6 SCMOS DEEP 3 * 3 * 3 Source/drain active to well edge Substrate/well contact active to well edge * Note: For analog and critic al digital designs, MOSIS re MOS channel widths (active under poly) for ON Semiconductor design s. Narrower devices, down to design rule minimum, will be functional, but their electrical characteristics will not scale, and their performance is not pred Design Technology Design Lambda (lambda) SCN3M, SCN3ME SCN3M_SUBM, SCN3ME_SUBM SCMOS Layout Rules - Thick Active THICK_ACTIVE is a layer used for those processes offering two different thicknesses of gate oxide (typically for the layout of transistors that operate at two different voltage levels). The ACTIVE layer is used to delineate all the active areas, regardless of gate oxide thickness. THICK_ACTIVE is used to mark those ACTIVE areas that will have the thicker gate oxide; ACTIVE areas outside THICK_ACTIVE will have the thinner gate oxide. THICK_ACTIVE by itself (not covering any ACTIVE polygon) is meaningless. SCMOS DEEP 24.1 Minimum width 24.2 Minimum spacing 24.3 Minimum ACTIVE overlap 24.4 Minimum space to external ACTIVE 24.5 Minimum poly width in a THICK_ACTIVE gate Every ACTIVE region is either entirely inside THICK_ACTIVE or entirely outside THICK_ACTIVE SCMOS Layout Rules - Pbase (Analog Option) The pbase layer is an active area that is implanted with the pbase implant to form the base of the NPN bipolar transist or. The base contact is enclosed in p- select. The emitter is an n-select region within (and on top of) the base. The -well that is the collector. The collector contact is a well contact, but the overlaps are larger. Active should not be used inside of Rule SCMOS DEEP All active contact 2 x 2 Minimum emitter select overlap of contact Minimum pbase overlap of emitter select Minimum pbase overlap of base select Minimum base select overlap of contact Minimum nwell overlap of pbase Minimum collector active overlap of contact Minimum nwell overlap of collector active Minimum select overlap of collector active CNPC with POLY_CAP tor are POLY and POLY_CAP1. The POLY_CAP1 must surround th e POLY everywhere; the area of the capacitor is the area of the POLY. POLY is physically on top of POLY_CAP1, so that contact to the POLY_CAP1 must be made in th e region where it extends beyond the POLY. The capacitor may be in the well or the substrate, but may not straddle SCMOS DEEP Minimum POLY_CAP1 width. This is lithographic; the minimum to build a real capacitor is greater than 12 lambda to POLY_CAP1 (neighboring _CAP1 to ACTIVE (all capacitors must be 23.4 Minimum overlap, POLY_CAP1 over POLY 23.5 Minimum overlap, POLY_CAP1 over CONTACT Minimum overlap, POLY over CONTACT (in a capacitor only; still 23.7 Minimum spacing, POLY to CONTACT-to-POLY_CAP1 23.8 Minimum spacing, unrela ted METAL1 to POLY_CAP1 23.9 Minimum spacing, SCMOS DEEP 2 Minimum spacing over field Minimum spacing over active Minimum gate extension of active Minimum active extension of poly ly to active SCMOS DEEP 4 4 Minimum spacing, SB to contact (no contacts allowed inside SB) to external active to external poly Resistor is poly inside SB; poly ends stick out for contacts 5 Minimum spacing of poly resistors (in a single SB region) 2 3 Minimum spacing, SB to poly (in a single active region) NOTE: Some processes do not support both silicide block over active and silicide block over poly. Refer to the individual process description pages. SCMOS DEEP Minimum select spacing to chan nel of transistor to ensure adequate source/drain width Minimum select overlap of active Minimum select overlap of contact Minimum select width and spacing (Note: P-select and N-select may be coincident, but must overlap) (not illustrated) The poly2 layer is a second polysilico n layer (physically above the standard, or first, poly layer). The oxide be tween the two polys is the capacitor dielectric. The capacitor area is the ar ea of coincident poly and electrode. SCMOS DEEP 7 3 5 Minimum spacing to active or well edge (not illustrated) 6 SCMOS Layout Rules - Poly2 for Transistor Same poly2 layer as for caps SCMOS DEEP or active contact The poly2 is contacted through the standa rd contact layer, similar to the first poly. The overlap numbers are larger, however. Contacts must be drawn orthogonal to the grid of the layout. Non-Manhattan contacts are not allowed. SCMOS DEEP Exact contact size 2 x 2 2 x 2     SCMOS DEEP 27.1 Minimum HR width 27.2 Minimum HR spacing Minimum spacing, HR to contact (no contacts allowed inside HR) 27.4 Minimum spacing, HR 27.5 Minimum spacing, HR to external poly2 Resistor is poly2 inside HR; poly2 ends stic k out for contacts, the entire resistor must be outside well and over field 27.7 Minimum poly2 width in resistor Minimum spacing of poly2 resistors (in a single HR region) 27.9 Minimum HR overlap of poly2 On 0.50 micron process (and all finer fe ature size processes), it is required that all features on the insulator layers (CONTACT, VIA, VIA2) must be of the ions for pads (or logos, or anything else); large openings must be replac ed by an array of standard sized openings. Contacts must be drawn orthog onal to the grid of the layout. Non- Manhattan contacts are not allowed. If your design cannot tolerate 1.5 la mbda contact overlap in 5.2, use the alternative rules which reduce the overlap but increase the spacing to surrounding features. Rules 5.1, 5.3, and 5.4, still apply and are unchanged. Simple Contact to Poly Alternative Contact to Poly SCMOS DEEP Exact contact contact spacing spacing to gate of transistor SCMOS DEEP spacing to other active (one active (many contacts) Simple Poly to Contact Alternative Contact to Poly SCMOS Layout Rules - Contact to Active If your design cannot handle the 1.5 lambda contact overlap in 6.2, use the alternative rules which reduce the overlap but increase the spacing to surrounding features. Rules 6.1, 6.3, and 6.4, still apply and are unchanged. Contacts must be drawn orthogonal to the grid of the layout. Non-Manhattan contacts are not allowed. Simple Contact to Active Alternative Contact to Active SCMOS DEEP Exact contact active overlap spacing to gate of transistor SCMOS DEEP diffusion active spacing to field spacing to field poly (many contacts) spacing to poly Simple Contact to Active Alternative Contact to Active SCMOS DEEP 3 3 1 Minimum spacing when either onal to the grid of the layout. Non-Manhattan vias are not allowed. SCMOS DEEP SCMOS DEEP 2 x 2 2 x 2 2 x 2 3 x 3 n/a 3 Minimum overlap by metal1 Minimum spacing to contact for technology codes mapped to processes that do not allow stacked vias (SCNA, SCNE, SCN3M, SCN3MLC) Minimum spacing to poly or active edge for technology codes mapped to processes that do not allow stacked vias (NOTE: list is not same as for 8.4) SCMOS DEEP SCMOS DEEP n/a 3 n/a 4 n/a 1 onal to the grid of the layout. Non-Manhattan vias are not allowed. SCMOS DEEP SCMOS DEEP 2x2 3x3 3 3 Minimum overlap by metal2 SCMOS DEEP SCMOS DEEP 15.1 Minimum width 15.2 Minimum spacing to metal3 15.3 Minimum overlap of via2 onal to the grid of the layout. Non-Manhattan vias are not allowed. SCMOS DEEP SCMOS DEEP 21.1 Exact size 21.2 Minimum spacing * Exception: Use lambda=4 for rule 21.2 only when using SCN4M_SUBM for Agilent/HP GMOS10QA 0.35 micron process SCMOS DEEP SCMOS DEEP Top Plate SCMOS DEEP Minimum Width, Capacitor Minimum Spacing (2 capaci tors sharing a single Rule applicability region extends beyond bottom apes (having no vias) Minimum bottom plate to other bottom plate 28.10 Minimum via separati on, on CAP_TOP_METAL Minimum (upward) via separation on bottom No vias from bottom plate down ward, directly under top plate 28.15 No active or passive circ uitry under capacitor region (SUBM and DEEP) onal to the grid of the layout. Non-Manhattan vias are not allowed. SCMOS DEEP SCMOS DEEP 3x3 3x3 3 3 SCMOS DEEP SCMOS DEEP 26.1 Minimum width 26.3 Minimum overlap of Via4 SCMOS Layout Rules - Via5 (SUBM and DEEP) onal to the grid of the layout. Non-Manhattan vias are not allowed. SCMOS DEEP 29.1 Exact size 3 x 3 4 x 4 29.2 Minimum spacing SCMOS DEEP 30.1 Minimum width 30.3 Minimum overlap of Via5 Minimum spacing when either Note that rules in this sect ion are in units of microns, lambda. They are not "true" design rules, but they do ma ke good practice rules. Unfortunately, design rules since pads are process- specific. Minimum bonding passivation opening Minimum pad spacing to active, poly or poly2